The invention relates to field effect transistor structures, and more particularly to temperature-compensated field effect transistor circuits and to inverting CMOS circuits having trip points or switching points that are compensated for variations in temperature and are relatively independent of certain manufacturing process parameter variations.
MOS field effect transistors (MOSFETs) produce drain currents that vary considerably with temperature. The MOSFET threshold voltages are heavily dependent on various manufacturing process parameters, especially the thicknesses of the gate oxide and the doping levels of the semiconductor region in which the MOSFET source and drain regions are diffused. MOSFET threshold voltages also are quite dependent upon the temperature of the device. Those skilled in the art know that MOSFETs are widely used in manufacture of high density, high performance integrated circuits. CMOS (complementary metal oxide semiconductor) integrated structures include both P-channel and N-channel MOSFETs configured to produce very high speed, low power, high performance integrated circuits. It is usually desirable to interface CMOS integrated circuits with input circuitry and output circuitry that is implemented in other integrated circuit technologies, especially the TTL (transistor-transistor logic) technology, which is capable of producing large output currents that may be necessary to drive large line capacitances and large output loads. The logical "0" and 1" levels of standard TTL circuits vary considerably. The typical range of values for a TTL logical "0" level is 0.8 volts to zero volts. A typical range of values for a TTL "1" level is 3.5 volts to 2.7 volts. Those skilled in the art know that it is very difficult to design an economical CMOS input buffer that is of adequately high speed and can properly respond to "worst case" values of the above ranges of TTL input levels. This is because the "trip point" or "switching point" of a typical CMOS inverter structure varies considerably with circuit temperature and CMOS manufacturing parameters, so that "worst case" circuit design of TTL compatible CMOS input inverters is very difficult. Further compounding the problem is the fact that sometimes it is desirable to operate CMOS circuits at power supply voltages other than ground and +5 volts, which is the standard TTL power supply voltage. CMOS circuits have the characteristic that they can operate effectively over a wide range of power supply voltages, but the percentage variation in a CMOS inverter switching point or trip point is almost proportional to the percentage variation in the power supply voltage. As soon as the power supply voltage (V.sub.DD) of a typical CMOS circuit is increased, it becomes impossible to drive that circuit with standard TTL logic levels. In order to provide good noise immunity for a logic circuit, including a CMOS logic circuit, it is sometimes desirable to provide hysteresis in the input circuitry of an integrated circuit chip. This is commonly done by using input latch circuits instead of non-latching input buffers. However, latch circuits are more complex and more expensive, especially if they are to be responsive to worst case TTL input voltage levels. Those skilled in the art know that providing hysteresis in a CMOS input circuit further complicates the already-difficult design problems encountered in making any CMOS circuit TTL compatible.
Those skilled in the art have utilized various modifications of standard MOS and CMOS manufacturing processes to selectively alter MOS threshold devices to achieve effective interfacing of TTL input signals to MOS and/or CMOS integrated circuits. However, alteration of any standard manufacturing process to accomplish a specific goal, for example, selectively altering MOS threshold voltages of a production process, is generally viewed as unacceptably costly and disruptive.
Despite 15 years of progress in the industry in the area of effectively interfacing TTL logic levels to MOS and CMOS circuitry, there still remains a largely unmet need for a truly economical, fast, TTL CMOS input circuit for shifting TTL input signals, which input circuit is quite independent of MOS manufacturing parameters (such as gate oxide thickness and channel doping levels) that affect MOSFET threshold voltages, which is relatively independent of temperature, which is relatively independent of MOS power supply voltages applied thereto, and which also has relatively high noise immunity.